This invention relates to the field of digital communications, and in particular clock synchronization in systems employing a backplane bus.
In switching systems where several cards are connected to a common data bus, it is important that clock distribution and synchronization be done such that re-arrangements in the clock distribution do not affect data transport over the common data bus. Standards, such as the ECTF H.110 standard, describe the implementation of a common data bus and a clocking scheme to ensure that no data disruptions occur due to clocking re-arrangements.
The ECTF H.110 standard defines timing devices within the system as “primary master”, “secondary master” or “slave”. The “primary master” and “secondary master” devices are capable of synchronizing to a network reference clock and driving one of the two independent backplane bus clock/frame pulse pairs. The backplane bus clock is 8.192 MHz while the backplane bus frame pulse is 8 kHz. The “slave” devices use the main backplane bus clock and frame pulse, the “A” clocks for synchronization to the backplane bus. The “A” clocks are driven by the “primary master” and are derived from a local network reference or a system wide network reference. A second pair consisting of a backplane bus clock and frame pulse, the “B” clocks are used as a backup clock on the backplane. The “B” clocks are driven by the “secondary master”. During normal operation, the “secondary master” and “slaves” are synchronized to the “A” clocks. When the “A” clocks becomes unreliable, the “slave” devices switch from using the “A” clocks to the “B” clocks for synchronization to the backplane bus. To ensure that during the switch from the “A” clocks to the “B” clocks, no data is lost, the “B” clocks must be phase locked with a minimum phase offset to the “A” clocks when the “A” clocks are reliable. When the “B” clocks are the main clocks on the backplane, the “secondary master” device that drives the “B” clocks switches from using the “A” clocks to using a network clock as its reference without disrupting data traffic on the backplane bus.
In order to meet all the requirements of synchronization and clock switching without the loss of data, the “secondary master” device must use a Phase Locked Loop (PLL) that can track the “A” clocks closely even in the presence of jitter. Therefore the “secondary master” should pass the jitter on the “A” clocks on to the “B” clocks. While not strictly required by the ECTF H.110 standard, it is also preferable for the “primary master” to attenuate jitter from the network reference clock while driving the “A” clocks. However, in order for the “Secondary master” to track the jitter on the “A” clocks, the PLL driving the “B” clocks may not attenuate the jitter. Since a “secondary master” or “slave” can become a “primary master”, the DPLLs in these devices must track the “A” clocks continuously. Also, they must be able to switch from one input reference to another and at the same time switch from no jitter attenuation to jitter attenuation without disrupting the backplane clock and frame pulse.
Prior art implementations have not been able to provide these mixed jitter attenuation requirements without disrupting data during clock re-arrangements.